SNIST.Mtech.VLSI.DSCE.2012

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Sunday, 31 March 2013

Recent Materials


CPLD
  • FPGA Architectures overview
  • Vending Machie (Verilog- Class)
  • EDA tools
  • FBGA global routing based on a new congestion metric.
  • FPGA Routing Architectures
  • FPGA placement and Routing Algorithm
  • Fast FPGA based pipe lined Digit-Serial/Parallel Multipliers
  • FPGA Design Flow Overview
DSD
  • Fault Detection Techniques***
  • PLA Folding
  • Switching and Finite Automata Theory
  • Sequential Circuit Synthesis 2 (incompletely specified machines)
ADSP
  • Structures of Discrete Time Systems-1
  • Discrete Time Systems
  • Structures of Discrete Time Systems -2 
  • Multirate Digital Signal Processing
  • Multirate Signal processing
VLSI
  • Modern VLSI Design (Text book for Floor Planning etc)
  • Clocking Disciplines
  • Sequential Systems Clocking Disciplines
  • Sequential Systems
  • Sequential systems Latches and registers
  • Chip Planning
  • Global Routing and Switch box Routing
  • Timing Issues in Digital Circuits(Clock Skew etc)
Assignment Questions CPLD and VLSI

Posted by SnistMtechVlsiDsce2012 at Sunday, March 31, 2013 No comments:
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