Recent Materials and Photo Copies

• CPLD Case Studies
• DSD
• CPLD
• DSD Merger Chart Methods
• CPLD Design Process And Flows
• FPGA 1
• FPGA 2

CPLD UNITWISE MATERIALS (By Prasad Acharya Sir)

ADC UNITWISE PPTS (by Lavanya madam)

VLSI 

• Unit 5
• Unit 6

Verilog LAB and Useful Web Sites For LAB

• Verilog Codes for Different Counters
• Verilog Coding Guidelines
• Verilog PPT
• Verilog HDL Coding

Useful WEB Sites

• http://www.asic.co.in/Index_files/verilogexamples.htm#link62
• http://ece451web.groups.et.byu.net/cadence-help/verilog.html#Anchor-Example-35067
• http://vlsiupdatez.blogspot.in/2012_02_01_archive.html
• http://www.asic-world.com/examples/verilog/
• http://electrofriends.com/category/source-codes/digital-electroninc/verilog-hdl/